Sample Questions

For a CMOS inverter, the transition slope of Vout vs Vin DC characteristics can be increased
(steeper transition) by:

Increasing W/L of PMOS transistor

Increasing W/L of NMOS transistor

Increasing W/L of both transistors by the same factor

Decreasing W/L of both transistor by the same factor


Minimum number of 2input NAND gates that will be required to implement the function: Y = AB + CD + EF is

4

5

6

7


Consider a twolevel memory hierarchy system M1 & M2. M1 is accessed first and on miss M2 is accessed. The access of M1 is 2 nanoseconds and the miss penalty (the time to get the data from M2 in case of a miss) is 100 nanoseconds. The probability that a valid data is found in M1 is 0.97. The average memory access time is:

4.94 nanoseconds

3.06 nanoseconds

5.00 nanoseconds

5.06 nanoseconds


Interrupt latency is the time elapsed between:

Occurrence of an interrupt and its detection by the CPU

Assertion of an interrupt and the start of the associated ISR

Assertion of an interrupt and the completion of the associated ISR

Start and completion of associated ISR


Which of the following is true for the function (A.B + A’.C + B.C)

This function can glitch and can be further reduced

This function can neither glitch nor can be further reduced

This function can glitch and cannot be further reduced

This function cannot glitch but can be further reduced


For the two flipflop configuration below, what is the relationship of the output at B to the clock frequency?

Output frequency is 1/4^{th} the clock frequency, with 50% duty cycle

Output frequency is 1/3^{rd} the clock frequency, with 50% duty cycle

Output frequency is 1/4^{th} the clock frequency, with 25% duty cycle

Output frequency is equal to the clock frequency


The voltage on Node B is:
 0
 10
 –10

A CPU supports 250 instructions. Each instruction opcode has these fields:
 The instruction type (one among 250)
 A conditional register specification
 3 register operands
 Addressing mode specification for both source operands
The CPU has 16 registers and supports 5 addressing modes. What is the instruction opcode length in bits?
 32
 24
 30
 36

In the iterative network shown, the output Yn of any stage N is 1 if the total number of 1s at the inputs starting from the first stage to the Nth stage is odd. (Each identical box in the iterative network has two inputs and two outputs). The optimal logic structure for the box consists of:

One AND gate and one NOR gate
 One NOR gate and one NAND gate
 Two XNOR gates
 One
XOR gate


Consider a circuit with N logic nets. If each net can be stuckat either values 0 and 1, in how many ways can the circuit be faulty such that only one net in it can be faulty, and such that upto all nets in it can be faulty?

2 and 2N
 N and 2^N
 2N and 3^N1
 2N and 3N

 In the circuit shown, all the flipflops are identical. If the
setup time is 2 ns, clock>Q delay is 3 ns and hold time is 1 ns, what
is the maximum frequency of operation for the circuit?
a. 200 MHz
b. 333 MHz
c. 250 MHz
d. None of the above 
Which of the following statements is/are true?
I. Combinational circuits may have feedback, sequential circuits do not.
II. Combinational circuits have a ‘memoryless’ property, sequential circuits do not.
III. Both combinational and sequential circuits must be controlled by an external clock.
 I only
 II and III only
 I and II only
 II only

Consider an alternate binary number representation scheme, wherein the number of ones M, in a word of N bits, is always the same. This scheme is called the MoutofN coding scheme. If M=N/2, and N=8, what is the efficiency of this coding scheme as against the regular binary number representation scheme? (As a hint, consider that the number of unique words represent able in the latter representation with N bits is 2^N. Hence the efficiency is 100%)

Close to 30%
 Close to 50%
 Close to 70%
 Close to 100%


A CPU supports 4 interrupts I1, I2, I3 and I4. It supports priority of interrupts. Nested interrupts are allowed if later interrupt is higher priority than previous one. During a certain period of time, we observe the following sequence of entry into and exit from the interrupt service routine:
I1startI2startI2endI4startI3startI3endI4endI1end
From this sequence, what can we infer about the interrupt routines?
 I3 > I4 > I2 > I1
 I4 > I3 > I2 > I1
 I2 > I1; I3 > I4 > I1
 I2 > I1, I3 > I4 > I2 > I1

I decide to build myself a small electric kettle to boil my cup of tea. I need 200 ml of water for my cup of tea. Assuming that typical tap water temperature is 25 C and I want the water boiling in exactly one minute, then what is the wattage required for the heating element?
[Assume: Boiling point of water is 100 C, 1 Calorie (heat required to change 1 gm of water by 1 C)= 4 joules, 1 ml of water weighs 1 gm.]
 Data given is insufficient
 800 W
 300 W
 1000 W
 250 W

The athletics team from REC Trichy is traveling by train. The train slows down, (but does not halt) at a small wayside station that has a 100 mts long platform. The sprinter (who can run 100 mts in 10 sec) decides to jump down and get a newspaper and some idlis. He jumps out just as his compartment enters the platform and spends 5 secs buying his newspaper that is at the point where he jumped out. He then sprints along the platform to buy idlis that is another 50 mts. He spends another 5 secs buying the idlis. He is now just 50 mts from the other end of the platform where the train is moving out. He begins running in the direction of the train and the only other open door in his train is located 50 mts behind the door from where he jumped. At what(uniform) speed should the train be traveled if he just misses jumping into the open door at the very edge of the platform?
Make the following assumptions

He always runs at his peak speed uniformly
 The train travels at uniform speed
 He does not wait (other than for the idlis & newspaper) or run baclwards
 Data given is insufficient

4 m/s
 5 m/s
 7.5 m/s
 10 m/s


State which of the following gate combinations does not form a universal logic set:
 2input AND + 2input OR
 2to1 multiplexer
 2input XOR + inverter
 3input NAND

For the circuit shown below, what should the function F be, so that it produces an output of the same frequency (function F1), and an output of double the frequency (function F2).
 F1= NOR gate and F2= OR gate

F1=NAND gate and F2= AND gate
 F1=AND gate and F2=XOR gate
 None of the above

The FSM (finite state machine) below starts in state Sa, which is the reset state, and detects a particular sequence of inputs leading it to state Sc. FSMs have a few characteristics. An autonomous FSM has no inputs. For a Moore FSM, the output depends on the present state alone. For a Mealy FSM, the output depends on the present state as well as the inputs. Which of the statements best describes the FSM below?
 It has two states and is autonomous

The information available is insufficient
 It is a Mealy machine with three states
 It
is a Moor machine with three states

In the circuit given below, the switch is opened at time t=0. Voltage across the capacitor at t=infinity is:
 2V
 3V
 5V
 7V

What is the functionality represented by the following circuit?
 y= ! (b+ac)
 y= ! (a+bc)
 y= ! (a(b+c))
 y=
! (a+b+c)

The value (0xdeadbeef) needs to stored at address 0x400. Which of the below ways will the memory look like in a big endian machine:
0x403 0x402 0x401 0x400
a. be ef de ad
b. ef be ad de
c. fe eb da ed
d. ed da eb fe

In a given CPUmemory subsystem, all accesses to the memory take two cycles. Accesses to memories in two consecutive cycles can therefore result in incorrect data transfer. Which of the following access mechanisms guarantees correct data transfer?
 A read operation followed by a write operation in the next cycle.

A write operation followed by a read operation in the next cycle.
 A NOP between every successive reads & writes
 None of the above

An architecture saves 4 control registers automatically on function entry (and restores them on function return). Save of each registers costs 1 cycle (so does restore). How many cycles are spent in these tasks (save and restore) while running the following unoptimized code with n=5:
Void fib(int n)
{
if((n==0)  (n==1)) return 1;
return(fib(n1) + fib(n2));
}
 120
 80
 125
 128

The maximum number of unique Boolean functions F(A,B), realizable for a two input (A,B) and single output (Z) circuit is:
 2
 6
 8